DIN EN 61523-2:2003-06
Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries (IEC 61523-2:2002); German version EN 61523-2:2002, text in English
| Fecha edición: |
2003-06-01
En Vigor
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| Idiomas disponibles: | Alemán, Inglés |
| Resumen: | This standard specifies the pre-layout delay calculation method for CMOS1 ASIC Libraries which contains cell based primitives and memories to be used during the pre-layout design phase of Logic simulation, Timing verification, and Logic synthesis. Diese Norm legt das Vorentwicklungsverfahren für die Laufzeitberechnung von CMOS-ASIC-Bibliotheken, die Grundzellen und Speicher beinhalten, fest. Diese Bibliotheken werden für die Vorentwicklungsphase von Logiksimulation, Zeitverhalten und Logiksynthese verwendet. |
| Keywords: | Chips|Computerized control|Definitions|Delay circuits|Delay time|Design calculations|Electrical engineering|Integrated circuit technology|Integrated circuits|Integrated memory circuits|Semiconductor devices|Specification |
| ICS: | 31.200 - Circuitos integrados. Microelectrónica |
| CTN: | |
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Equivalencia Internacional |
Idéntica EN 61523-2:2002 Idéntica IEC 61523-2:2002 |
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Reemplazo Normas |
Reemplaza a DIN IEC 93/110/CD:1999-12 |
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